Semiconductor memory devices, such as erasable, programmable, read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), and flash erasable programmable read-only memories (FEPROMs) are erasable and reusable, and are employed in various commercial electronic devices, such as computers, cellular telephones and digital cameras. There has recently evolved flash memory devices termed mirrorbit devices, which do not contain a floating gate electrode. In mirrorbit devices, the gate electrode is spaced apart from the substrate by an oxide/nitride/oxide (ONO) stack, such as a silicon oxide/silicon nitride/silicon oxide stack. In such devices the charge is contained within the nitride layer of the ONO stack. The relentless drive for miniaturization has led to the fabrication of flash memory devices comprising transistors having a gate width of about 150 nm and under, and gate structures spaced apart by a gap of 225 nm or less. Conventional practices comprise forming a sidewall spacer on side surfaces of the gate stack, thereby reducing the gate gap to about 25 nm.
As device dimensions shrink into the deep sub-micron regime, vulnerability to mobile ion contamination, such as hydrogen degradation, increases. The inability to adequately getter or reduce the generation of mobile ion contaminants, such as hydrogen ions, results in a neutralization of electrons and, hence, leakage causing programming loss as well as a charge gain causing reappearance of erased information.
As device features plunge into the deep submicron regime, interconnect technology is transitioning from aluminum-based to copper-based metallurgy. This technological evolution has come about through the adoption of damascene and dual-damascene process flows involving electrolytic copper plating and chemical mechanical polishing (CMP) techniques. The technological benefits of Cu, such as reduced RxC delay are clear; however, various reliability issues have evolved. For example, due to Cu diffusion through interlayer dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Ti—TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology employing a diffusion barrier layer (capping layer). For example, conventional practices comprise forming a damascene opening in an interlayer dielectric, depositing a barrier layer, such as TaN, lining the opening and on the surface of the interlayer dielectric, filling the opening with Cu or a Cu alloy layer, implementing CMP, and forming a silicon nitride capping (diffusion barrier) layer on the exposed surface of the Cu or Cu alloy. It was found, however, that oxides on the upper surface of the inlaid Cu or Cu alloy can prevent adequate adhesion of the capping layers. Consequently, the capping layer is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing electromigration and stress migration resistance.
In applying Cu interconnect technology to flash memory devices, additional problems occur, particularly as dimensions shrink into the deep sub-micron regime. A Cu or Cu alloy is typically deposited in an opening formed in an interlayered dielectric (ILD), such as a dual damascene opening comprising a lower via or contact hole connected to an upper trench, forming an overburden. Chemical mechanical polishing (CMP) is implemented such that the overburden is planarized and the upper surface of the inlaid copper is substantially coplanar with the upper surface of the ILD. In accordance with conventional practices, the inlaid Cu or Cu alloy is annealed to allow grain growth in the deposited copper, thereby relieving stress accumulated during damascene filling. Conventionally, such annealing is conducted in a forming gas atmosphere comprising nitrogen (N2) and about 4 vol. % hydrogen (H2) at a temperature of about 250° C. However, it was found that such back end processing generated and/or accelerated the diffusion of hydrogen ions into underlying flash memory devices adversely impacting data retention by causing a charge loss.
Accordingly, there exists a need for a method of fabricating semiconductor memory devices with improved reliability, increased operating speed and reduced leakage. There exists a particular need for methodology enabling the fabrication of flash memory devices, such as microbit devices, with improved data retention and improved reliability, and Cu interconnects.